1. Field of the Invention
The present invention relates to the fabrication of integrated circuits. More particularly, the invention relates to a process for depositing dielectric layers on a substrate.
2. Background of the Related Art
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore""s Law), which means that the number of devices that will fit on a chip doubles every two years. Today""s fabrication plants are routinely producing devices having 0.35 xcexcm and even 0.18 xcexcm feature sizes, and tomorrow""s plants soon will be producing devices having even smaller geometries.
In order to further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and insulators having low dielectric constants (k, wherein k less than 4.0) to reduce the capacitive coupling between adjacent metal lines. Low k dielectrics have been deposited by both spin-on glass methods and by chemical vapor deposition (CVD) techniques as described in International Publication Number WO 99/41423. Liner/barrier layers including capping layers have been deposited adjacent to the low k dielectric layers to prevent diffusion of byproducts such as moisture from the low k dielectric layer onto the conductive material as described in International Publication Number WO 99/41423, and from the ambient environment into the low k dielectric.
For example, moisture generated during the formation of a low k insulator readily diffuses to the surface of the conductive metal and increases the resistivity of adjacent conductive metal surface. To prevent interlayer diffusion, barrier/liner layers are deposited between the layers and are typically formed from conventional silicon based materials, such as silicon nitride, that block the diffusion of byproducts and/or prevent the diffusion of metal layers into the low k material. However, the barrier/liner layers typically have dielectric constants that are significantly greater than 4.0, such as silicon nitride with a dielectric constant of about 7, and the high dielectric constants can result in a combined insulator layer that does not significantly reduce the dielectric constant.
One approach to forming low k layers is to deposit a high porosity, low density film to obtain dielectric constants that approach the dielectric constant of air, i.e., kxcx9c1. An example of a low k porous film deposition process is described in U.S. Pat. No. 5,858,457, issued to Brinker et al. Brinker et al. discloses a method for forming a low dielectric constant films having high film porosity by the deposition of a sol-gel precursor on a substrate, followed by selective evaporation of components of the sol-gel precursor to form supramolecular assemblies. The assemblies are then formed into ordered porous films by the oxidative pyrolysis of the supra-molecular templates at approximately 400xc2x0 C. However, in the Brinker at al. patent, the pyrolysis step requires about four hours to calcinate the sol-gel into a porous film. Such lengths of time are incompatible with the increasing demand for higher processing speeds in modem semi-conductor manufacturing.
High porosity silica-based films, such as the silicon oxide films described in Brinker et al. above, have poor diffusion resistance to charged mobile ions, especially alkali ions such as sodium and potassium formed in sol-gel precursors. These charge ions readily diffuse into and through the film under the influence of applied electric fields and increase the film""s conductivity and result in polarization of the film as well as an increase the dielectric constant of the film. Therefore, the transport of charged mobile ions is deleterious to the low dielectric constant insulator films used for integrated circuit multi-level interconnections.
Additionally, silica-based porous films are often hydrophilic and aggressively absorb moisture from the surrounding environment. If water, which has a dielectric constant (k) of about 78, is absorbed by the porous film, then the low k dielectric properties of the porous film can be detrimentally affected. Often, these hydrophilic films are annealed to remove moisture, but this is only a temporary solution in a deposition process since the films are still sensitive to moisture contamination following this procedure. Additionally, annealing is often a time consuming process which adds to the processing time of the substrate and results in lower through put rates. Generally, to limit moisture contamination in hydrophilic films, the film is turned from a hydrophilic film to a hydrophobic film by a silylation process AND by depositing a capping or passivation layer to prevent moisture contamination in the porous film.
One problem in depositing capping layers on porous films is that porous films, such as spin-coating and spray-coating porous films are deposited at atmosphere pressure, i.e., greater than about 300 Torr, and the capping layer is typically deposited by a plasma enhanced chemical vapor deposition (PECVD) process carried out at vacuum pressures, i.e., less than about 100 Torr. Such vacuum processes and atmosphere processes are typically carried out in separate vacuum and atmosphere processing systems or cluster tool apparatuses, wherein transfer from one processing system or apparatus to another exposes the porous films to contamination. Cluster tools are modular, multi-chamber, integrated processing system having a central substrate handling module and a number of peripheral process chambers, where introduced substrates undergo a series of process steps sequentially in various process chambers to form integrated circuits. Cluster tools have become generally accepted as effective and efficient equipment for manufacturing advanced microelectronic devices.
FIG. 1 illustrates a vacuum cluster tool 10 having multiple single substrate processing chambers 12 mounted on a centralized vacuum chamber, called a transfer chamber 18, for transferring substrates from a substrate cassette located in one or more load lock chambers 20, to one or more process chambers 12. This particular tool is shown to accommodate up to four (4) single substrate processing chambers 12 positioned radially about the transfer chamber. A cluster tool similar to that shown in FIG. 1 is available from Applied Materials, Inc. of Santa Clara, Calif. The transfer of the substrates between the process chambers 12 is typically managed by a substrate handling module 16 located in a central transfer chamber 12. After the substrates are processed, they are moved back through the load lock chamber 20 and into substrate cassettes where the substrates can be moved to the next system for additional processing. Various processes, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), etch, can be performed in the process chambers 12.
Typically, atmosphere processing cluster tools and vacuum processing cluster tools have not been integrated. Vacuum processing tools require the retention of a vacuum or reestablishment of a vacuum by vacuum pumping during various process steps in a process cycle. This vacuum requirement lends to longer processing times and a lower through-put rate than compared to atmosphere processing tools which has made integration of these systems unattractive. However, transfer of substrates between the cluster tools can result in contamination of the process substrates which is very problematic in the transfer of films sensitive to contamination, such as porous films. Currently in the industry, there are no cluster tools that combine the deposition of low k dielectric materials and capping materials under both ambient atmosphere and near vacuum processing conditions.
Therefore, there remains a need for a process to deposit ion diffusion resistant low k dielectric materials with high substrate throughput.
The present invention provides a method and apparatus for depositing a mesoporous silicon oxide layer having a low dielectric constant. In accordance with one aspect of the invention, the invention provides for a process for depositing a mesoporous oxide layer containing phosphorus and having a low dielectric constant. The mesoporous film preferably has a phosphorus concentration of a phosphorus compound, such as phosphorus pentaoxide (P2O5) of between about 2% and about 8% by weight. The mesoporous silicon oxide layer is produced by depositing and curing a phosphorus containing sol-gel precursor to form a oxide film having interconnecting pores of uniform diameter, preferably in a cubic phase structure, then exposing the film to an inert gas anneal at a temperature of between about 200xc2x0 C. and about 450xc2x0 C., or an oxidizing atmosphere containing a reactive oxygen species at a temperature between about 200xc2x0 C. and about 400xc2x0 C., to remove the surfactant and form a phosphorus doped mesoporous oxide film. The mesoporous oxide film preferably has a porosity of at least 50% and a dielectric constant between about 1.6 and about 2.2. The mesoporous film may also be used as a inter-metal dielectric layer.
The phosphorus containing sol-gel precursor preferably comprises a silicon/oxygen compound, a phosphorus containing acid solution, an organic solvent, water, and a surfactant. Phosphorus may also be introduced into the sol-gel precursor by the addition or substitution of a phosphonic acid ligand, (xe2x80x94PO(OH)2), on a silicon bearing chemical precursor, by a phosphorus based acid solution comprising a phosphorus based acid, which may further include volatile inorganic acids and/or organic acids, and by a phosphorus based component of a surfactant, preferably a phosphate of an alcohol-terminated surfactant selected from the group comprising p-(CH3)3CCH2C6H4CH2(OCH2CH2)Nxe2x80x94OH, p-(CH3)3COC6H4CH2(OCH2CH2)Nxe2x80x94OH, (CH3)3CCH2C(CH3)2C6H4(OCH2CH2)Nxe2x80x94OH, CH3(CH2)Kxe2x80x94OH, CH3(CH2)I(CH2CH2O)Jxe2x80x94OH, HO(CH2CH2O)M(CH2C(CH3)HO)L(CH2CH2O)MH, and fluorinated derivatives thereof, and combinations thereof, where N is an integer from 6 to 12, preferably 8, K is an integer from 13 to 17, I is an integer from 6 to 15, J is an integer from 20 to 106, and L is an integer from 20 to 80.
In another aspect of the invention a mesoporous oxide film may be formed on a substrate by forming a first sol-gel precursor comprising a first silicon/oxygen compound, an organic acid, a first organic solvent, water, and a first surfactant, forming a second sol-gel precursor comprising a second silicon/oxygen compound, a phosphorus based acid, a second organic solvent, water, and a second surfactant, mixing the first and second sol-gel precursors to form a mixed sol-gel precursor, depositing the mixed sol-gel precursor on the substrate, curing the deposited mixed sol-gel precursor to form an oxide film, and exposing the oxide film to a surfactant removing process to form a mesoporous oxide film. Preferably the first and second sol-gels are mixed in a first sol-gel precursor to second sol-gel precursor ratio of between about 1:1 and about 10:1. Preferably, the mesoporous oxide film has a phosphorus concentration of a phosphorus compound, such as phosphorus pentaoxide (P2O5) of between about 2% and about 8% by weight.
In yet another aspect of the invention, a method is provided for forming a dual damascene structure comprising depositing a first etch stop on a substrate, depositing a first phosphorus doped mesoporous oxide film on the first etch stop, depositing a second etch stop on the first phosphorus doped mesoporous oxide film, depositing a second phosphorus doped mesoporous oxide film on the second etch stop, depositing a third etch stop on the second phosphorus doped mesoporous oxide film, etching the third etch stop and second phosphorus doped mesoporous oxide film to define a vertical interconnect opening, and etching the second etch stop, the first phosphorus doped mesoporous oxide film, and the first etch stop through the vertical interconnect opening to further define the vertical interconnect, thereby exposing the substrate, and etching the third etch stop and the second phosphorus doped mesoporous oxide film to define a horizontal interconnect and form a dual damascene feature. Preferably, the mesoporous oxide film has a phosphorus concentration of a phosphorus compound, such as phosphorus pentaoxide (P2O5) of between about 2% and about 8% by weight.